(1) Field of the Invention
The invention relates to a method of photolithographic etching of metal lines, and more particularly, to a method of photolithographic etching of sub-quarter micron metal lines without undercutting in the manufacture of integrated circuits.
(2) Description of the Prior Art
It is desired for metal lines to have a vertical profile. This is not always easy to achieve, especially for sub-quarter micron metal lines. FIG. 1 illustrates in cross-sectional representation a partially completed integrated circuit device. Semiconductor substrate 40 contains semiconductor devices structures, not shown. A metal line stack is shown on the substrate. Barrier metal layer 44 (for example, titanium/titanium nitride) is on the bottom of the stack. The metal layer 46, such as AlCu, overlies the barrier layer. An antireflective coating (ARC) 48 is at the top of the stack. Photoresist mask 50 is used in etching the metal line.
In order to improve lithographic resolution in the formation of sub-quarter micron metal lines, the photoresist layer must become thinner. However, if the photoresist layer is too thin, the top corner 52 of the metal line may be damaged during the etching of a high aspect ratio metal line. Therefore, it is necessary to use a hard mask during metal etching in sub-quarter micron technology to protect the metal top corners without using a thicker photoresist mask.
FIG. 2 illustrates a partially completed integrated circuit device as in FIG. 1 except that an oxide hard mask 49 has been formed overlying the ARC layer. Conventionally, the etchant gases are BCl3, Cl2, and N2. These gases have been found to be insufficient in producing a passivation layer on the sidewalls of the AlCu lines which would prevent Cl2 erosion and undercutting during etching. The undercutting 53 is illustrated in FIG. 2.
One proposed solution to the undercutting problem is the use of SF6 gas in the overetch step to react with titanium from the barrier layer and AlCu to form AlFx or TiFx as a passivation layer. However, SF6 is also the etching gas used in the tungsten etchback process. Tungsten plugs are likely to underlie the metal lines in the substrate, as illustrated in FIG. 3. Especially at the endcap of the metal line, as shown in FIG. 3, the SF6 etchant gas will damage the integrity of the tungsten plug 54.
U.S. Pat. No. 5,460,693 to Moslehi uses a fluorinated layer as a mask instead of photoresist. An oxide is formed on the unexposed areas of the fluorinated layer to form a hard oxide mask. U.S. Pat. No. 5,591,676 to Hughes et al teaches etching a fluorinated polymer using a hard oxide mask. U.S. Pat. No. 5,369,053 to Fang teaches using an oxide hard mask under a thin photoresist layer and etching the underlying metal using both a fluorine-based etchant and a chlorine-based etchant. U.S. Pat. No. 5,350,484 to Gardner et al teaches a method of implanting ions into an exposed area of metal and then selectively removing the implanted metal.
A principal object of the present invention is to provide an effective and very manufacturable method of etching metal lines.
Another object of the present invention is to provide a method of etching metal lines without undercutting of the metal lines.
A further object of the present invention is to provide a method of etching metal lines having a vertical etching profile.
Yet another object of the present invention is to provide a method of etching metal lines wherein the integrity of an underlying tungsten plug is preserved.
A still further object of the present invention is to provide a method of etching metal lines using fluorine-doped silicate glass as a hard mask.
In accordance with the objects of this invention a new method of etching metal lines using fluorine-doped silicate glass as a hard mask is achieved. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A metal layer is deposited overlying the insulating layer. A layer of fluorine-doped silicate glass is deposited overlying the metal layer wherein the fluorine-doped silicate glass layer acts as a hard mask. The hard mask is covered with a layer of photoresist. The photoresist layer is exposed to actinic light and developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer not covered by the patterned hard mask is etched away to form metal lines whereby fluorine ions released from the patterned hard mask form a passivation layer on the sidewalls of the metal lines thereby preventing undercutting of the metal lines resulting in metal lines having a vertical profile. The photoresist mask is removed and fabrication of the integrated circuit is completed.
Also in accordance with the objects of the invention, an integrated circuit device having a fluorine-doped silicate glass hard mask is achieved. Semiconductor device structures lie in and on a semiconductor substrate having an insulating layer thereover. A tungsten plug extends through the insulating layer to contact one of the semiconductor device structures. A metal line stack overlies the tungsten plug wherein the metal line stack comprises a barrier layer contacting the tungsten plug, a metal layer overlying the barrier layer, an antireflective coating layer overlying the metal layer, and a fluorine-doped silicate glass hard mask overlying the antireflective coating layer. A passivation layer overlies the metal line stack to complete the integrated circuit device.